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SSCD IIT Kanpur · Basic Analog Building Blocks · 69 videos

EE613: High-frequency analog circuit design (2025)

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Videos in this playlist

Thumbnail for Cadence demo: Systematic design of a two-stage Miller OTA & tackling the gate parasitic capacitance

Cadence demo: Systematic design of a two-stage Miller OTA & tackling the gate parasitic capacitance

Thumbnail for Lecture 37: To do post schematic: Good layout practices & handling package parasitics

Lecture 37: To do post schematic: Good layout practices & handling package parasitics

Thumbnail for Lecture 36: Intro to Low drop-out regulators (LDO); Understanding LDO as a 2-stage OTA in feedback

Lecture 36: Intro to Low drop-out regulators (LDO); Understanding LDO as a 2-stage OTA in feedback

Thumbnail for Lecture 35(2): Self-biased bandgap reference

Lecture 35(2): Self-biased bandgap reference

Thumbnail for Lecture 35(1): Fractional band-gap reference

Lecture 35(1): Fractional band-gap reference

Thumbnail for Lecture 34: Bandgap reference

Lecture 34: Bandgap reference

Thumbnail for Lecture 33(2): Method of non-linear currents for estimating weak non-linearities

Lecture 33(2): Method of non-linear currents for estimating weak non-linearities

Thumbnail for Lecture 33(1): Using negative feedback to combat non-linearity

Lecture 33(1): Using negative feedback to combat non-linearity

Thumbnail for Lecture 32: Non-linearity in fully-differential ckts; Techniques to realize a linear transconductor

Lecture 32: Non-linearity in fully-differential ckts; Techniques to realize a linear transconductor

Thumbnail for Lecture 31: Noise in fully differential circuits; Scaling analog circuits for noise and bandwidth

Lecture 31: Noise in fully differential circuits; Scaling analog circuits for noise and bandwidth

Thumbnail for Lecture 30: Input referred noise & offset in 5-transistor OTA and cascodes

Lecture 30: Input referred noise & offset in 5-transistor OTA and cascodes

Thumbnail for Lecture 29: Input referred noise voltage & current: Example calculations

Lecture 29: Input referred noise voltage & current: Example calculations

Thumbnail for Lecture 28: Intro to noise; Input referred noise voltage and current

Lecture 28: Intro to noise; Input referred noise voltage and current

Thumbnail for Lecture 27(2): Common-mode to differential-mode conversion in diff amp & offset due to mismatch

Lecture 27(2): Common-mode to differential-mode conversion in diff amp & offset due to mismatch

Thumbnail for Lecture 27(1): Mismatch in current mirror

Lecture 27(1): Mismatch in current mirror

Thumbnail for Lecture 26(2): Random mismatch & process variations; Relative mismatch; Pelgrom's model

Lecture 26(2): Random mismatch & process variations; Relative mismatch; Pelgrom's model

Thumbnail for Lecture 26(1): Fully differential two stage feedforward compensated OTA with current reuse

Lecture 26(1): Fully differential two stage feedforward compensated OTA with current reuse

Thumbnail for Lecture 25: Common-mode rejection by CMFB & output impedance due to CMFB

Lecture 25: Common-mode rejection by CMFB & output impedance due to CMFB

Thumbnail for Lecture 24(2): Fully differential two-stage Miller compensated OTA with CMFB design considerations

Lecture 24(2): Fully differential two-stage Miller compensated OTA with CMFB design considerations

Thumbnail for Lecture 24(1): CMFB variants (contd.)

Lecture 24(1): CMFB variants (contd.)

Thumbnail for Lecture 23: Common-mode feedback variants

Lecture 23: Common-mode feedback variants

Thumbnail for Lecture 22(2): Need for common-mode feedback in fully differential opamps

Lecture 22(2): Need for common-mode feedback in fully differential opamps

Thumbnail for Lecture 22(1): Power supply rejection ratio of 5-transistor OTA; Need for differential signaling

Lecture 22(1): Power supply rejection ratio of 5-transistor OTA; Need for differential signaling

Thumbnail for Lecture 21(2): Nested Miller & Feedforward compensation

Lecture 21(2): Nested Miller & Feedforward compensation

Thumbnail for Lecture 21(1): So far in this course... A 26 minute recap

Lecture 21(1): So far in this course... A 26 minute recap

Thumbnail for Lecture 20(2): Feedforward compensation; comparison with Miller compensation

Lecture 20(2): Feedforward compensation; comparison with Miller compensation

Thumbnail for Lecture 20(1): Ahuja compensation (contd.): Circuit implementation

Lecture 20(1): Ahuja compensation (contd.): Circuit implementation

Thumbnail for Lecture 19(2): Ahuja compensation: Pole locations; Intuition for complex poles in Ahuja compensation

Lecture 19(2): Ahuja compensation: Pole locations; Intuition for complex poles in Ahuja compensation

Thumbnail for Lecture 19(1): Miller compensation: Adding a series resistor to eliminate RHP zero

Lecture 19(1): Miller compensation: Adding a series resistor to eliminate RHP zero

Thumbnail for Lecture 18: Miller OTA: Circuit implementation; Need for DC negative feedback; Systematic offset

Lecture 18: Miller OTA: Circuit implementation; Need for DC negative feedback; Systematic offset

Thumbnail for Lecture 17(2): Rough design example of the two-stage Miller compensated OTA

Lecture 17(2): Rough design example of the two-stage Miller compensated OTA

Thumbnail for Lecture 17(1): Introducing the two-stage Miller compensated OTA

Lecture 17(1): Introducing the two-stage Miller compensated OTA

Thumbnail for Lecture 16(3): Understanding Miller & feed-forward compensation from root-locus

Lecture 16(3): Understanding Miller & feed-forward compensation from root-locus

Thumbnail for Lecture 16(2): Time-domain perspective on why LHP zeros are good & RHP zeros are bad for stability

Lecture 16(2): Time-domain perspective on why LHP zeros are good & RHP zeros are bad for stability

Thumbnail for Lecture 16(1): Time-domain understanding on why more poles makes the closed-loop system unstable?

Lecture 16(1): Time-domain understanding on why more poles makes the closed-loop system unstable?

Thumbnail for Lecture 15: Deriving phase margin from root locus; Loop gain more than one & 180deg phase: stable?

Lecture 15: Deriving phase margin from root locus; Loop gain more than one & 180deg phase: stable?

Thumbnail for Lecture 14(3): Need for multi-stage OTAs; 1st order systems in negative feedback

Lecture 14(3): Need for multi-stage OTAs; 1st order systems in negative feedback

Thumbnail for Lecture 14(2): Poles & zeros in telescopic cascode

Lecture 14(2): Poles & zeros in telescopic cascode

Thumbnail for Lecture 14(1): Detecting uncoupled poles; Summary on when to write pole as conductance by cap.

Lecture 14(1): Detecting uncoupled poles; Summary on when to write pole as conductance by cap.

Thumbnail for Lecture 13(4): Poles and zeros in cascode

Lecture 13(4): Poles and zeros in cascode

Thumbnail for Lecture 13(3): 5-transistor OTA: Summary of poles & zeros in differential mode

Lecture 13(3): 5-transistor OTA: Summary of poles & zeros in differential mode

Thumbnail for Lecture 13(2): Zeros in differential mode in the five-transistor OTA (pole-zero cancellation)

Lecture 13(2): Zeros in differential mode in the five-transistor OTA (pole-zero cancellation)

Thumbnail for Lecture 13(1): Pole locations in the five-transistor OTA

Lecture 13(1): Pole locations in the five-transistor OTA

Thumbnail for Lecture 12(5): Intuition for high-freq. pole. Why can't Miller effect be used for high-freq. pole?

Lecture 12(5): Intuition for high-freq. pole. Why can't Miller effect be used for high-freq. pole?

Thumbnail for Lecture 12(4): Miller effect: Intuition behind low-frequency pole location in common-source config.

Lecture 12(4): Miller effect: Intuition behind low-frequency pole location in common-source config.

Thumbnail for Lecture 12(3): Poles & zeros in common-source configuration

Lecture 12(3): Poles & zeros in common-source configuration

Thumbnail for Lecture 12(2): Poles & zeros by inspection in common-drain configuration

Lecture 12(2): Poles & zeros by inspection in common-drain configuration

Thumbnail for Lecture 12(1): Poles & zeros (recap); example of an uncontrollable and unobservable state

Lecture 12(1): Poles & zeros (recap); example of an uncontrollable and unobservable state

Thumbnail for Lecture 11(2): Test to find presence of zeros; Origin of zeros; Calculating zero location

Lecture 11(2): Test to find presence of zeros; Origin of zeros; Calculating zero location

Thumbnail for Lecture 11(1): Pole location; When can poles be approx as ratio of conductance & cap.?

Lecture 11(1): Pole location; When can poles be approx as ratio of conductance & cap.?

Thumbnail for Lecture 10(2): Gain-boosted cascode; Gm boosting

Lecture 10(2): Gain-boosted cascode; Gm boosting

Thumbnail for Lecture 10(1): Slew rate of a folded cascode OTA

Lecture 10(1): Slew rate of a folded cascode OTA

Thumbnail for Lecture 9(1): Motivation for folded cascode opamp; Telescopic cascode opamp in unity feedback

Lecture 9(1): Motivation for folded cascode opamp; Telescopic cascode opamp in unity feedback

Thumbnail for Lecture 9(2): Merits of folded-cascode: Input common-mode range, output range, unity feedback swings

Lecture 9(2): Merits of folded-cascode: Input common-mode range, output range, unity feedback swings

Thumbnail for Lecture 8: Telescopic cascode: DC op. point, dc gain, input common-mode range & output swing limits

Lecture 8: Telescopic cascode: DC op. point, dc gain, input common-mode range & output swing limits

Thumbnail for Lecture 7: Systematic design of analog circuits using look-up tables (gm/Id based) & design example

Lecture 7: Systematic design of analog circuits using look-up tables (gm/Id based) & design example

Thumbnail for Lecture 6(3): Common mode & differential mode response of the 5-transistor OTA

Lecture 6(3): Common mode & differential mode response of the 5-transistor OTA

Thumbnail for Lecture 6(2): Impedances at each node in the 5-transistor OTA

Lecture 6(2): Impedances at each node in the 5-transistor OTA

Thumbnail for Lecture 6(1): Example problems; Defining the impedance looking up and down into a node

Lecture 6(1): Example problems; Defining the impedance looking up and down into a node

Thumbnail for Lecture 5(2): Slew rate of the five-transistor OTA

Lecture 5(2): Slew rate of the five-transistor OTA

Thumbnail for Lecture 5(1): Step response of a VCCS vs. VCVS in negative feedback with a capacitive load

Lecture 5(1): Step response of a VCCS vs. VCVS in negative feedback with a capacitive load

Thumbnail for Lecture 4(3): Input common-mode range and output range calculations in the five-transistor OTA

Lecture 4(3): Input common-mode range and output range calculations in the five-transistor OTA

Thumbnail for Lecture 4(2): Why input common-mode & output range are relevant in opamps?

Lecture 4(2): Why input common-mode & output range are relevant in opamps?

Thumbnail for Lecture 4(1): Summary of differential amplifier; OTA vs opamp

Lecture 4(1): Summary of differential amplifier; OTA vs opamp

Thumbnail for Lecture 3(3): The 5-transistor amplifier: Short-circuit transconductance & output resistance

Lecture 3(3): The 5-transistor amplifier: Short-circuit transconductance & output resistance

Thumbnail for Lecture 3(2): The five-transistor amplifier: DC operating point

Lecture 3(2): The five-transistor amplifier: DC operating point

Thumbnail for Lecture 3(1): Differential amplifier: Differential mode & common-mode half circuits

Lecture 3(1): Differential amplifier: Differential mode & common-mode half circuits

Thumbnail for Lecture 2: Recap of Common source, drain & gate configurations; Re-intro to differential amplifier

Lecture 2: Recap of Common source, drain & gate configurations; Re-intro to differential amplifier

Thumbnail for Lecture 1: MOSFET recap: Strong inversion vs. weak inversion vs. linear region; Universality of VCCS

Lecture 1: MOSFET recap: Strong inversion vs. weak inversion vs. linear region; Universality of VCCS