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SSCD IIT Kanpur
·
Basic Analog Building Blocks
·
25 videos
EE698G: Circuit design for frequency and phase synthesis (2024)
Original playlist on YouTube
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Videos in this playlist
Lecture 1: Introduction
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Lecture 3: Delay-locked loop, tunable delay line
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Lecture 4: Delay tuning using varactors, phase detector
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Lecture 5: Phase detectors -II
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Lecture 6: Phase detectors - III
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Lecture 7: Locking in a DLL
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Lecture 8: Locking nonidealities in a DLL
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Lecture 10: Charge pumps - II
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Lecture 11: Charge pumps - III, transistor mismatches, modelling a DLL
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Lecture 12: Small signal phase domain model of the DLL - I
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Lecture-13: S-domain model analysis for DLL, Discrete time modeling of DLL
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Lecture 14: Discrete time DLL model, Type-II DLL, DLL applications
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Lecture 15: Noise, PSD, thermal and flicker noise
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Lecture 16: Jitter definitions, jitter characterizations
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Lecture 17: Relationship between phase noise and jitter
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Lecture 18: Phase noise/jitter analysis in VCO, inverter and delay line
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Lecture 19: Jitter in delay line vs ring oscillator; Oscillators-I
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Lecture 20: Oscillators - II
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Lecture 21: Oscillators--III
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Lecture 22: Oscillators-IV
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Lecture 23: Oscillators-V
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Lecture 24: Design of a ring oscillator
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Lecture 25: Design of ring oscillator-II, Introduction to PLL
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Lecture 26: Phase-locked loop - II
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Lecture 27: Phase-locked loop - III
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