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SSCD IIT Kanpur
·
Basic Analog Building Blocks
·
29 videos
EE698G (2026): Phase and Frequency Synthesis
Original playlist on YouTube
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Videos in this playlist
EE698G lec26: Phase-locked loops III
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EE698G lec25: Phase-locked loops II
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EE698G lec24: Phase-locked loops I
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EE698G lec23: Oscillators-IV (LC oscillators)
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EE698G lec22: Oscillators-III (LC oscillators)
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EE698G lec21: Oscillators-II
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EE698G lec20: Phase noise- III, Introduction to oscillators
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EE698G lec19: Phase noise, jitter - II
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EE698G lec18: Phase noise, jitter - I
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EE698G lec17: DLL applications, introduction to noise
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EE698G lec16: Discrete-time small-signal phase-domain model for the DLL
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EE698G lec15: DLL transfer functions
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EE698G lec14: Small-signal phase domain model of a DLL
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EE698G 2026 lec13(2): Modelling the DLL for analysis
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EE698G lec13(1): Mismatches in charge pump, VCDL
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EE698G lec12: Charge pump implementation - II
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EE698G lec11: Static phase offset in DLL, charge pump implementation-I
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EE698G lec10: Locking non-idealities in a DLL
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EE698G lec9: Locking in a DLL
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EE698G lec8: Phase detectors - III, charge pump
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EE698G lec7: Phase detectors - II
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EE698G lec6: Phase detectors - I
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EE698G lec5: Voltage-controlled delay lines - II
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EE698G lec4: Introduction to delay-locked loop, VCDL
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EE698G lec3: TDC, PVT variation, stabilizing the delay
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EE698G lec1(4): True time delay vs delaying the edges
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EE698G lec1(3): Relationship between phase and delay
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EE698G lec1(2): Relationship between phase and frequency
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EE698G lec1: Introduction - clock/delay requirements in IC design
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