arrow_back All playlists

SSCD IIT Kanpur · Basic Analog Building Blocks · 24 videos

EE619A: VLSI System Design

Original playlist on YouTube arrow_outward

Videos in this playlist

Thumbnail for Lecture 1: Introduction

Lecture 1: Introduction

Thumbnail for Lecture 2: PN junction, MOS capacitor, MOS transistor, current in a MOS transistor

Lecture 2: PN junction, MOS capacitor, MOS transistor, current in a MOS transistor

Thumbnail for Lecture 3: Short channel effects, PMOS transistor

Lecture 3: Short channel effects, PMOS transistor

Thumbnail for Lecture 4: Capacitances in MOS transistor, inverter

Lecture 4: Capacitances in MOS transistor, inverter

Thumbnail for Lecture 5: Inverter characteristics, inverter with resistive load

Lecture 5: Inverter characteristics, inverter with resistive load

Thumbnail for Lecture 6: Delay, power and area of inverter with resistive load, CMOS inverter

Lecture 6: Delay, power and area of inverter with resistive load, CMOS inverter

Thumbnail for Lecture 7: Mid-point voltage and VTC of CMOS inverter

Lecture 7: Mid-point voltage and VTC of CMOS inverter

Thumbnail for Lecture 8: Propagation delay of a CMOS inverter

Lecture 8: Propagation delay of a CMOS inverter

Thumbnail for Lecture 9: Elmore delay model, power consumption in an inverter

Lecture 9: Elmore delay model, power consumption in an inverter

Thumbnail for Lecture 10: Power consumption in CMOS inverter

Lecture 10: Power consumption in CMOS inverter

Thumbnail for Lecture 11: Ring oscillator, process variation, combinational logic

Lecture 11: Ring oscillator, process variation, combinational logic

Thumbnail for Lecture 12: Combinational circuits - sizing, capacitance, delay

Lecture 12: Combinational circuits - sizing, capacitance, delay

Thumbnail for Lecture 13: Delay of combinational circuits

Lecture 13: Delay of combinational circuits

Thumbnail for Lecture 14: Verilog

Lecture 14: Verilog

Thumbnail for Lecture 15: Linear delay model

Lecture 15: Linear delay model

Thumbnail for Lecture 16: Sizing gates for optimal delay

Lecture 16: Sizing gates for optimal delay

Thumbnail for Lecture 17: Optimal number of stages for minimum delay, reducing logical effort

Lecture 17: Optimal number of stages for minimum delay, reducing logical effort

Thumbnail for Lecture 18: Pseudo NMOS logic, pass transistors

Lecture 18: Pseudo NMOS logic, pass transistors

Thumbnail for Lecture 19: MUX implementation, dynamic circuits

Lecture 19: MUX implementation, dynamic circuits

Thumbnail for Lecture 20: Dynamic circuits

Lecture 20: Dynamic circuits

Thumbnail for Lecture 21: Sequential circuits

Lecture 21: Sequential circuits

Thumbnail for Lecture 22: Timing constraints for a flipflop

Lecture 22: Timing constraints for a flipflop

Thumbnail for Lecture 24: Dynamic flip-flops

Lecture 24: Dynamic flip-flops

Thumbnail for Lecture 25: Timing Analysis

Lecture 25: Timing Analysis