arrow_back All playlists

SSCD IIT Kanpur · Basic Analog Building Blocks · 45 videos

EE370: Digital Electronics (2025)

Original playlist on YouTube arrow_outward

Videos in this playlist

Thumbnail for EE370 Lec1: Overview of digital design implementation (Introductory lecture)

EE370 Lec1: Overview of digital design implementation (Introductory lecture)

Thumbnail for EE370 lec2: Verilog (I)

EE370 lec2: Verilog (I)

Thumbnail for EE370 lec3: Verilog - (II)

EE370 lec3: Verilog - (II)

Thumbnail for EE370 lec4: Verilog - (III)

EE370 lec4: Verilog - (III)

Thumbnail for EE370 lec5: Verilog (IV)

EE370 lec5: Verilog (IV)

Thumbnail for EE370 lec6: Mealy vs Moore state machines

EE370 lec6: Mealy vs Moore state machines

Thumbnail for EE370 lec7: State minimization in FSM, FSMD

EE370 lec7: State minimization in FSM, FSMD

Thumbnail for EE370 lec 8 (1) : Introduction to FSM and datapath

EE370 lec 8 (1) : Introduction to FSM and datapath

Thumbnail for EE370 lec 8 (2): FSMD for greatest common divisor computation

EE370 lec 8 (2): FSMD for greatest common divisor computation

Thumbnail for EE370 lec11(1) : Design of controller for a faster algorithm for GCD computation

EE370 lec11(1) : Design of controller for a faster algorithm for GCD computation

Thumbnail for EE370 lec11(2) : Verilog implementation of GCD algorithm

EE370 lec11(2) : Verilog implementation of GCD algorithm

Thumbnail for EE370 lec12: Timing analysis in a digital design

EE370 lec12: Timing analysis in a digital design

Thumbnail for EE370 lec13: Static timing analysis (II)

EE370 lec13: Static timing analysis (II)

Thumbnail for EE370 lec14 (1): Review of an FSMD for modulo operation

EE370 lec14 (1): Review of an FSMD for modulo operation

Thumbnail for EE370 lec14( 2): STA with contamination and propagation delays

EE370 lec14( 2): STA with contamination and propagation delays

Thumbnail for EE370 lec15: ROM, PAL, PLA

EE370 lec15: ROM, PAL, PLA

Thumbnail for EE370 lec16( 1): Tutorial problem of setup, hold and clk-to-q delays of a D-flipflop

EE370 lec16( 1): Tutorial problem of setup, hold and clk-to-q delays of a D-flipflop

Thumbnail for EE370 lec16( 2): Wired OR in ROM (one implementation), SPLD, CPLD, FPGA

EE370 lec16( 2): Wired OR in ROM (one implementation), SPLD, CPLD, FPGA

Thumbnail for EE370 lec17: Transistor as a switch

EE370 lec17: Transistor as a switch

Thumbnail for EE370 lec19: Capacitance in a MOSFET

EE370 lec19: Capacitance in a MOSFET

Thumbnail for EE370 lec21: Voltage Transfer Characteristics of a CMOS inverter

EE370 lec21: Voltage Transfer Characteristics of a CMOS inverter

Thumbnail for EE370 lec22: Mid-point voltage in a CMOS inverter

EE370 lec22: Mid-point voltage in a CMOS inverter

Thumbnail for EE370 lec23: Mid-point voltage (II), Noise margin from VTC

EE370 lec23: Mid-point voltage (II), Noise margin from VTC

Thumbnail for EE370 lec24: Delays in a CMOS inverter (I)

EE370 lec24: Delays in a CMOS inverter (I)

Thumbnail for EE370 lec25: Delays in a CMOS inverter (II)

EE370 lec25: Delays in a CMOS inverter (II)

Thumbnail for EE370 lec26(1): Delays in a CMOS inverter (III)

EE370 lec26(1): Delays in a CMOS inverter (III)

Thumbnail for EE370 lec26(2): Elmore Delay

EE370 lec26(2): Elmore Delay

Thumbnail for EE370 lec27: Power consumption in CMOS inverters

EE370 lec27: Power consumption in CMOS inverters

Thumbnail for EE370 lec28: Trade-offs in optimizing power consumption in a CMOS inverter

EE370 lec28: Trade-offs in optimizing power consumption in a CMOS inverter

Thumbnail for EE370 lec29: Sizing an inverter chain for optimal delay

EE370 lec29: Sizing an inverter chain for optimal delay

Thumbnail for EE370 lec30: Overview of CMOS inverter layout, combinational logic

EE370 lec30: Overview of CMOS inverter layout, combinational logic

Thumbnail for EE370 lec31: Sizing transistors in combinational circuits

EE370 lec31: Sizing transistors in combinational circuits

Thumbnail for EE370 lec32: Propagation and contamination delays in a combinational circuit

EE370 lec32: Propagation and contamination delays in a combinational circuit

Thumbnail for EE370 lec33(1): Fall propagation delay in N-input NAND gate

EE370 lec33(1): Fall propagation delay in N-input NAND gate

Thumbnail for EE370 lec33(2): Deriving PUN from PDN using graphs

EE370 lec33(2): Deriving PUN from PDN using graphs

Thumbnail for EE370 lec33(3): Pass transistor logic

EE370 lec33(3): Pass transistor logic

Thumbnail for EE370 lec34(1): Pass transistor logic-II

EE370 lec34(1): Pass transistor logic-II

Thumbnail for EE370 lec34(2): Latches and flip-flops

EE370 lec34(2): Latches and flip-flops

Thumbnail for EE370 lec35: Latch implementation using transmission gates; Bistable element

EE370 lec35: Latch implementation using transmission gates; Bistable element

Thumbnail for EE370 lec36(1): Timing parameters of a flipflop built using TGs and bistable elements

EE370 lec36(1): Timing parameters of a flipflop built using TGs and bistable elements

Thumbnail for EE370 lec36(2): Introduction to adder circuits

EE370 lec36(2): Introduction to adder circuits

Thumbnail for EE370 lec37: Ripple carry adder

EE370 lec37: Ripple carry adder

Thumbnail for EE370 lec38: Carry bypass adder

EE370 lec38: Carry bypass adder

Thumbnail for EE370 lec39(1): Carry select adder

EE370 lec39(1): Carry select adder

Thumbnail for EE370 lec39(2): EE370 done! What next?

EE370 lec39(2): EE370 done! What next?