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SSCD IIT Kanpur
·
Basic Analog Building Blocks
·
18 videos
EE 698G: Circuit design for frequency and phase synthesis (2023)
Original playlist on YouTube
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Videos in this playlist
Lecture 1: Introduction
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Lecture 2: Flash TDC, PVT variation, Introduction to DLL
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Lecture 3: Variable delay lines
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Lecture 4: Variable delay lines, Phase detectors - Multiplier, S&H, XOR
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Lecture 5: SR latch based PD, PFD
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Lecture 6: Locking in a DLL
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Lecture 7: Locking nonidealities: False locking, harmonic locking, SPO
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Lecture 8: Charge pump implementation
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Lecture 9: Gate-switched charge pump, mismatches, modelling the DLL
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Lecture 10: Small signal phase domain model of the DLL
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Lecture 11: Small signal analysis of DLL (Open and closed loop transfer functions)
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Lecture 12: Discrete time model for the DLL
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Lecture 13: Type-II DLL, DLL applications, noise review
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Lecture 14: Noise review, introduction to phase noise and jitter, jitter definitions
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Lecture 15: Characterizing jitter, relationship between jitter and phase noise, jitter PSD
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Lecture 16: Relationship between phase noise PSD and clock signal PSD; reporting phase noise
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Lecture 17: Phase noise, jitter in inverter, delay line and ring oscillator (qualitative analysis)
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Lecture-18: Introduction to oscillators
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