arrow_back From playlist: EE698I: Mixed-signal IC design (2023)
SSCD IIT Kanpur

Lecture 17: Pipelined ADC; Redundancy to tackle comparator offset; 1.5-bit (M+0.5) bit stage;

This lecture is in our queue for curation. AnalogLore summaries are hand-verified — this video will be fully annotated soon.